Carbon Nanotube Transistor Compact Model
نویسندگان
چکیده
In this paper, we describe the development of device models and tools for the design of the carbon nanotube FET (CNFET). Both HSPICE model and Verilog-A model for CNFET including typical device/circuit level non-idealities have been developed. They can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor.
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